Method for fabricating an integrated circuit structure

ABSTRACT

In one embodiment, the present invention provides a method of treating a dielectric layer 24. First, the dielectric layer is heated while being subjected to an O 2  plasma. After that, the dielectric layer is heated while being subject to an ozone environment. This method can be useful in forming a capacitor 12 dielectric 24. In turn, the capacitor could be used in a DRAM memory device.

This is a Non Provisional application filed under 35 USC 119(e) andclaims priority of prior provisional, Ser. No. 60/036,481 of inventorTsu, et al., filed Jan. 31, 1997.

RELATED PATENT APPLICATION

The following co-assigned patent applications are related to the presentinvention and are hereby incorporated herein by reference.

    ______________________________________                                        Pat. or   Filing       Issue    Attorney                                        Ser. No. Date Date Docket                                                   ______________________________________                                        09/014,724                                                                              01/28/98              TI-21537                                        09/014,484 01/28/98  TI-21973                                                 5,972,769 12/18/97 10/26/99 TI-21704                                        ______________________________________                                    

FIELD OF THE INVENTION

This invention relates generally to the fabrication of semiconductordevices and specifically to a method of treating a dielectric which canbe used in the formation of an integrated circuit capacitor.

BACKGROUND OF THE INVENTION

DRAM memory cell sizes continue to decrease. For example, memories whichstore 64 Mb of information are now in production with plans to implement256 Mb and 1 Gb memories soon. These high density memories have a designrule of a minimum 0.35 μm or less. As the cells get smaller,conventional dielectrics such as nitride/oxide (N/O) can hardly supplysufficient storage capacitance. This requirement is due to the fact thatN/O materials have a low dielectric constant of about seven. In general,a simple formula can be used to express capacitance, namely C_(s) /A=ε₀ε_(r) /t, where C_(s) represents storage cell capacitance, A is thetotal surface area of the capacitor, t is the dielectric film thickness,and ε₀ and ε_(r) stands for vacuum and relative permitivities,respectively. To increase capacitance, complicated cell structuresincluding multiple fins and disks have been proposed to increase thesurface area between the plates and dielectric. These complex cellstructures, however, are difficult to fabricate and, therefore, notsuitable for manufacturing.

Storage capacitors using high dielectric constant (k) materialsincluding tantalum pentoxide (Ta₂ O₅), barium strontium titanate (BST),strontium titanate (SrTiO₃), and lead zirconium titanate (PZT) have beenproposed as dielectrics for simple cell structures including simplestacked cell (STC). The high dielectric constant of these materials givesufficient storage capacitance. Unfortunately, high dielectric constantmaterials including BST, SrTiO₃, and PZT are difficult to form usingstandard processing techniques. For example, it is difficult to controldielectric composition.

Although Ta₂ O₅ has a dielectric constant of about 25 compared withBST's dielectric constant of about 400, the Ta2O₅ capacitors are mucheasier to fabricate than BST capacitors. Ta₂ O₅ capacitors, however,usually have high leakage current density. Therefore, a need exists fora process of forming a high dielectric capacitor which overcomes many ofthe problems of the prior art.

SUMMARY OF THE INVENTION

The present invention provides a method for forming an improveddielectric material. This material can be used in an integrated circuitcapacitor which can in turn be used in a wide variety of devicesincluding dynamic random access memories (DRAMs). In one aspect, thepresent invention proposes a two step anneal after dielectric depositionto improve the dielectric film properties as well as the interfacebetween the dielectric and underlying conductor. This process results inlower leakage current density and lower effective oxide thicknessattributed to the increase of the dielectric constant.

In one embodiment, the present invention provides a method of treating adielectric layer. First, the dielectric layer is heated while beingsubjected to an O₂ plasma. After that, the dielectric layer is heatedwhile being subject to an ozone environment. This method can be usefulin forming a capacitor dielectric. In turn, the capacitor could be usedin a DRAM memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

The above features of the present invention will be more clearlyunderstood from consideration of the following descriptions inconnection with accompanying drawings in which:

FIG. 1a is a cross-sectional view of a DRAM cell which can utilize thestructure of the present invention;

FIG. 1b is a schematic diagram of the structure of FIG. 1a.

FIGS. 2a-2c are diagrams of a DRAM circuit which can utilize thecapacitor of the present invention; and

FIGS. 3a-3i are cross-sectional views illustrating one process flow forforming a DRAM which utilizes the capacitor of the present invention;and

FIG. 4 is a table detailing an experimental test of capacitors builtusing the present invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and use of the various embodiments are discussed below indetail. However, it should be appreciated that the present inventionprovides many applicable inventive concepts which can be embodied in awide variety of specific contexts. The specific embodiments discussedare merely illustrative of specific ways to make and use the invention,and do not limit the scope of the invention.

FIG. 1a illustrates a simplified view of a first embodiment DRAM cell(actually two cells) which includes a capacitor which utilizes thestructure of the present invention. FIG. 1b is a schematic diagram ofthe DRAM cells of FIG. 1a. As will be clear to those familiar withDRAMs, the cross-sectional view and schematic diagram shown in FIGS. 1aand 1b appear similar to prior art devices. The composition of materialsand method of forming them, however, make the present invention uniquecompared with the prior art.

Referring now to FIGS. 1a and 1b together, each DRAM cell includes apass transistor 10 coupled in series with a capacitor 12. The gate 14 ofpass transistor 10 comprises one of the word lines WL of the memoryarray. (A memory array will be described in more detail with respect toFIG. 2a). A shared source/drain region 16 of each pass 10 is coupled tobit line 18. The other source/drain region 20 is coupled to the storagenode electrode 22 of capacitor 12. Capacitor 12 further includesdielectric layer 24 and cell plate 26.

A simplified schematic diagram of a DRAM array is illustrated in FIG.2a. As shown, a plurality of memory cells can be formed in an array ofrows and columns. FIG. 2a illustrates only six bit lines BL and fourword lines WL in what in actuality would likely be a much larger array.The pass transistor Q of each memory cell has a gate G coupled to a wordline WL and a source/drain region BLC (for bit line contact) coupled toa bit line BL. The transfer gate G of one pass transistor Q will beelectrically coupled to the word line WL for a number of other passtransistors.

FIG. 2a also illustrates some of the peripheral circuitry which would beincluded in a memory array. For example, each pair of bit lines BL andBL(bar) is coupled to a sense amplifier SA. The bit lines BL and BL(bar)are also coupled to input/outline lines I/O and I/O(bar) through selecttransistors Y₀ -Y₂. Other peripheral circuitry such as the row decoders,column decoders, address buffers, I/O buffers and so on are notillustrated here. For the purposes of this invention, the memory celland fabrication method are independent of the memory architecture.

As an example, the memory array can be designed as an asynchronousmemory or as a synchronous memory. A synchronous memory can be timedwith an internal clock (not shown) or an external clock (not shown). Thedevice can have a single external data terminal or multiple externaldata terminals (i.e., wide word). The array can include a total of 4megabits, 16 megabits, 64 megabits, 256 megabits, one gigabit or more.

A simplified block diagram of a memory device is shown in FIG. 2b. Theinternal device circuitry includes an array and peripheral circuitry.The array may be divided into a number of blocks depending upon thedevice architecture. Sense amplifiers may be interleaved within thearray blocks.

Several external terminals are illustrated in FIG. 2b. Address terminalsA₀, A₁, . . . , A_(n) are provided for receiving row and columnaddresses. These terminals may be multiplexed (i.e., a first address isapplied at a first time and a second address applied at a second time).A single data terminal D is also illustrated. This terminal may comprisean input, an output or an input/output. Other data terminals may also beincluded. For example, a wide word device will have multiple dataterminals. In general, these terminals are provided for receiving inputsignals from circuitry (not shown) external of the array and forproviding output signals to circuitry (not shown) external of the array.

FIG. 2b also illustrates a number of control/status signals. Thesesignals are used to operate the memory device. For example, anasynchronous memory device may be operated by applying chip select, rowaddress strobe and column address strobe signals. Other signals mayindicate whether a read or write operation is being performed. In asynchronous device, one of the control signals may be a clock signal.Status signals may provide information about the device to the externalsystem. For example, the device may include a signal indicating whethera refresh operation is taking place or which portion of the array isbeing accessed.

A memory array of the present invention could also be embedded in alarger integrated circuit device. An embedded memory is a memory arrayand its associated control circuitry on the same integrated circuit as asubstantial amount of logic. FIG. 2c has been included to illustrate asimple block diagram of an embedded memory. In this example, a DRAMarray is included along with a processor (e.g., microprocessor, digitalsignal processor, specialty processor, microcontroller), another memoryarray (e.g., SRAM, non-volatile memory such as EPROM, EEPROM, flashmemory, PROM, ROM, another DRAM array) and other logic circuitry. Theseparticular blocks have been chosen to illustrate the wide variety ofother logic which could be included. Any combination of the devicescould be included.

As applied to a DRAM, the present invention relates to an improvedstorage capacitor 12. Prior art capacitance has been increased by eitherincreasing the surface area between the two plates 22 and 26 ofcapacitor 12 or by using a high dielectric constant (high-k or HDC)material for the cell capacitor dielectric 24. Materials such astantalum pentoxide (Ta₂ O₅), barium strontium titanate or simply BST(Ba_(1-x) Sr_(x) TiO₃), strontium titanate (SrTiO₃) and lead zirconiumtitanate or simply PZT (Pb_(1-x) Zr_(x) TiO₃) have been proposed forsimple cell structures such as the simple stack cell (STC). Co-pendingpatent applications Ser. Nos. 09/014,724 (TI-21537) and 09/014,484(TI-21973) disclose non-planar capacitors which can be used with highdielectric constant materials. The capacitors of either of thesedisclosures can be utilized herein.

A method of forming a DRAM array will now be described with reference toFIGS. 3a-3i. This method is included to illustrate how the presentinvention could be easily incorporated in a DRAM process flow.

Referring now to FIG. 3a, a DRAM device 5 will be formed in asemiconductor substrate 30. The substrate is preferably a p-typesubstrate although n-type substrates could alternatively be used. Inaddition, substrate 30 need not be a substrate at all. In this context,a substrate can be a substrate, an epitaxially grown layer, a well (ortub or tank) formed in another layer, a semiconductor layer formed overan insulator (e.g., SOI, SOS) or any other semiconductor region.

FIG. 3a illustrates field isolation regions 32 and four word line/passgates 14. While illustrated with field isolation 32, it is also notedthat other isolation techniques such as trench isolation can be used.The regions 14b and 14c will form the gates of the two memory cellswhich will be illustrated in these drawings. Word lines 14a and 14d, onthe other hand, will serve as the pass transistors for gates in otherrows of the device. The gate regions 14 preferably comprise dopedpolysilicon but other conductive materials such as metals or stackedlayers of polysilicon and metals can be used.

In the preferred embodiment, each of the word lines 14 is surrounded bya nitride (e.g., Si₃ N₄) region 34. This region 34 can be used for aself-aligned contact (SAC) etch process as described below.

Referring now to FIG. 3b an insulating layer 36 is formed over thedevice. In the preferred embodiment, insulating layer 36 comprises anoxide layer (e.g., formed from the decomposition of tetraethyloxysilaneor TEOS) on a BPSG (borophosphosilicate glass) layer. Oxides formed fromTEOS tend to have better oxide properties than BPSG in terms ofbreakdown, leakage, and density. Hence, the oxide formed from TEOS isdeposited on top of BPSG in the preferred embodiment.

A plug 38 is formed within an insulating layer 36. Storage plate plugs38 can be formed, for example, through standard patterning and etching.In one example, the plug can be formed by use of a self-aligned contactetch. In this process, an etchant which removes oxide region 36 withoutremoving nitride region 34 is introduced in the area above the contact.The etchant will then expose the substrate 30 surface without exposingword lines 14. In this manner, the plug 38 can be formed withoutelectrically shorting to the word line 14. The plug 38 material can bedoped polysilicon or a metal. The nature of the plug is not critical tothe present invention.

Bit line regions 18 are formed in FIG. 3c. As illustrated, in thisexample, the two memory cells being fabricated will share a single bitline (see FIG. 2a for the electrical schematic). While it is notcritical to this invention, the bit line 18 may comprise any conductivematerial such as silicon or a metal.

Referring now to FIG. 3d, formation of the storage node 22 of thecapacitors is continued. An insulating layer 40 is formed over the bitlines 18. Using standard patterning and etching techniques, a contacthole is formed through insulating layer 40 to expose plug 38. Althoughnot illustrated, a self-aligned contact etch may be used. Subsequently asecond conductive layer or 22- base layer storage node is formed overthe insulating layer and so as to contact plugs 38.

In the preferred embodiment, base storage node layer 22' is depositedover the insulating region 40 and plug 38. Base metal layer 22' can beformed by chemical vapor deposition (CVD), physical vapor deposition(PVD), or plasma enhanced chemical vapor deposition (PECVD), asexamples. In the preferred embodiment, storage node layer 22' is amaterial that is relatively good for oxidation resistance and has highwork function. The preferred materials for base storage node metal layer22' are listed in Table 1. It is noted, however, than other metals mayalternatively be used. For example, other transition metals such asruthenium (Ru), iridium (Ir), and molybdenum (Mo), suicides such asW/TiN, W/WSi_(x), WSi_(x), Si_(x) /TiN, WSi_(x) N_(y), TaSi_(x),TaSi_(x) N_(y), TiSi_(x), TiSi_(x) N_(y), and conductive oxide materialsincluding ruthenium oxide (RuO₂), iridium oxide (IrO₂) and (La,Sr)CoO₃can be used for base storage node layer 22'. The base storage node layer22' can be formed from the same material as plug 38, but this is not arequirement. For example, a metal base electrode 22' can be formed overa polysilicon plug 38.

Referring now to FIG. 3c, a sacrificial layer 42 is formed over storagenode layer 22'. The composition of this layer 42 is not critical sinceit will be removed during subsequent processing (as illustrated in FIG.3g). In the preferred embodiment, an oxide (e.g., SiO₂) is used for thesacrificial layer 42. A photoresist (not shown) can be used to make thepatterned sacrificial layer 42 into a hard mask. This mask 42 can thenbe used to etch the base metal layer 22' as illustrated in FIG. 3e. Themasking layer 42 is patterned so as to protect the portion of layer 22'which will become part of the storage node 22.

Referring now to FIG. 3f, a second conductive layer 22" is formed overthe structure. In the preferred embodiment, layer 22" comprises aconformally deposited polysilicon material which will surround dummylayer 42. The conductive layer 22" preferably surrounds the top and sidesurfaces of the sacrificial region 42. The choices for the conductivelayer 22" are the same as those listed above for base layer 22'. In thepreferred embodiment, conductive layer 22" comprises the same materialas base layer 22". This feature, however, is not a requirement. In otherwords, conductive layer 22" can comprise a different material than baselayer 22'.

Referring now to FIG. 3g along with FIG. 3f, a portion of the conductivelayer 22" on the top surface of the sacrificial region 42 is removed.This removal will expose the top surface of the sacrificial region 22'but will leave a portion of the metal layer 22' on the side surfaces ofthe sacrificial region. In the preferred embodiment, this removal stepis accomplished with an anisotropic etch-back of metal layer 21'.Sacrificial region 42 can then be removed leaving a cylindrical storagenode 22. In the preferred embodiment, the storage node 22 is anelongated rectangle with rounded edges. Any shape, however, can becreated by the choice of patterning the sacrificial layer 22.

Specific methods of forming the storage node 22 are described inco-pending applications Ser. Nos. 09/014,724 (TI-21537) and 09/014,484(TI-21973). For example, in the first co-pending application, thestorage node is preferably polysilicon which is treated withself-aligned silicide process and then nitrided. In the secondco-pending application, the storage node is formed from a metal which isthen nitrided. Either of these embodiments or any other embodiment forforming a storage node can be used.

A multiple crown storage node is disclosed in U.S. Pat. No. 5,972,769(TI-21704). This structure can be used instead of the structuredescribed thus far.

Referring now to FIG. 3h, a dielectric layer 24 can be formed over thestorage node 22. Dielectric layer 24 can comprise an oxide, a nitride ora combination of the two (e.g., an oxide-nitride-oxide or oxide-nitridestack or oxynitride). The present invention can also use a wide varietyof other dielectrics including tantalum pentoxide (Ta₂ O₅), bariumstrontium titanate or simply BST (Ba_(1-x) Sr_(x) TiO₃), strontiumtitanate (SrTiO₃), strontium bismuth tantalate or simply SBT and leadzirconium titanate or simply PZT (Pb_(1-x) Zr_(x) TiO₃). In thepreferred embodiment, a high dielectric constant material (i.e., k>˜20)is used. For example, in one embodiment about 15 nm of Ta₂ O₅ isdeposited at about 400° C.

After the dielectric layer 24 is formed a two step anneal is performed.This two step post dielectric deposition anneal will improve thecapacitor electrical performance including the effective oxide thickness(T_(eff)) and leakage current density. The two-step anneals aretypically applied to as-deposited films. The first anneal, preferably O₂plasma, is used to render energetic O₂ ions to impinge the as-depositeddielectric films to enrich oxygen concentration and decomposehydrocarbons left in the as-deposited films. The second anneal,preferably an ozone anneal, with or without ultra-violet lightirradiation, is employed to remove oxygen plasma induced damage andresidual hydrocarbons.

The chemical composition of the dielectric layer will be unique comparedto prior art dielectrics. For example, consider an example where atantalum pentoxide dielectric is formed. Typically as-deposited Ta₂O_(x) is slightly oxygen deficient (i.e., x<5). The two step annealprocess of the present invention, however, can render an as-depositedTa₂ O_(x) material to become stoichiometric (i.e., x=5) or slightlyoxygen rich (i.e., x>5).

In the preferred embodiment, the crystal structure of dielectric layer24 will not change. It will remain in the amorphous phase since both theplasma treatment and the ozone anneal are performed at a temperature inthe range of about 20° C. to about 350° C. Even though the crystalstructure may remain amorphous, however, the density could be improveddue to the increased oxygen content.

In an alternative embodiment, the ozone anneal can be performed after acrystallization anneal. The crystallization anneal will transform anamorphous layer into a crystalline (e.g., polycrystalline) anneal. Forexample, dielectric layer 24 could be heated in an O₂ or N₂ O ambient toa temperature of about 700° C. The anneal could be performed either as afurnace anneal or as a rapid thermal anneal. This additional step couldimprove tantalum pentoxide capacitor performance, especially for ametal-insulator-semiconductor capacitor.

The two-step anneal process can be applied to as-deposited amorphous Ta₂O₅ films 24 on either semiconductor, ceramic, or metal bottom electrodes22. It is further noted that the present invention can be applied toother dielectrics such as BST, PZT, SBT, SrTiO₃, NO, ONO or others. Thepresent invention is especially useful with dielectrics grown frommetal-organic sources.

As illustrated in FIG. 3i, top electrode 26 is formed over dielectriclayer 24. Top electrode 26 can comprise just about any conductivematerial. The only criteria is that the electrode material be physically(e.g., adhesively, thermally) compatible with dielectric material 24.For example, electrode 26 can comprise Si (e.g., polysilicon), a metal(e.g., Al, Cu, Pd, Pt, Ru, Au, Ag, Ta, Ti, Mo, W), a silicide (e.g.,TaSi_(x), TiSi_(x), AlSi_(x), CoSi_(x), WSi_(x), MoSi_(x), an alloysilicide), a conductive nitride (e.g., TiN, TiAlN, TaSiN, WSiN, WN, MoN,RuN, SnN, ZrN), a conducive oxide (e.g., RuO₂, SnO, ZO, IrO), or otherconductive materials (e.g., a carbide such as tantalum carbide, a boridesuch as titanium boride).

It is noted that a number of additional steps will be required beforethe DRAM device is completed. For example, additional metal layer(s) canbe used for interconnects. Also, the drive with need a protectiveovercoat and packaging. Since these steps are not critical to thepresent invention, they will not be described here beyond theacknowledgment of their existence.

The materials and process options for forming a storage capacitor of thepresent invention are summarized in Table 1. It is noted that Table 1lists only some of the examples of the present invention and is notintended to encompass all possible embodiments.

                  TABLE 1                                                         ______________________________________                                        Element    Materials       Deposition Methods                                 ______________________________________                                        Bottom Electrode 22                                                                      W, Pt, Mo, metal alloy,                                                                       CVD,                                                  TaSiN, TiSiN, WSiN, plasma enhanced                                           MoSiN, TiAlN, WN, MoN, CVD, sputtering                                        metal alloy silicon nitride,                                                  doped poly Si                                                                Dielectric 24 Ta.sub.2 O.sub.5, Ba.sub.1-x Sr.sub.x TiO.sub.3, MOCVD,                                    Pb.sub.1-x Zr.sub.x TiO.sub.3, SrTiO.sub.3                                  plasma enhanced                                        MOCVD                                                                       Top Electrode 26 W, Pt, Mo, metal alloy, CVD,                                  TaSiN, TiSiN, WSiN, plasma enhanced                                           MoSiN, TiAlN, WN, MoN, CVD, sputtering                                        meal alloy silicon nitride,                                                   doped poly Si                                                              ______________________________________                                    

Embodiments of the present invention have been fabricatedexperimentally. To begin, N-type Si(100) wafers 30 were processed withTiN/sputtered W/WN/Ta₂ O₅ /Au. The details of the processing can befound above and in co-pending incorporated patent applications Ser. No.09/014,724 (TI-21537) and Ser. No. 09/014,484 (TI-21973). After Ta₂ O₅deposition, both O₂ plasma and O₃ anneals were performed. Gold was thenevaporated onto the Ta₂ O₅ dielectric for evaluation of a simple planarcapacitor. Since the interface between dielectric 24 bottom electrode 22and is most affected by oxidation during the Ta₂ O₅ processing, theleakage current density versus voltage was measured to determinecritical voltage V_(c). For these purposes, the critical voltage V_(c)is defined as the voltage with a leakage current density of 10⁻⁸ A/cm².The effective oxide thickness T_(eff) is derived and measured from theequation C/A=ε₀ *3.9/T_(eff) where the capacitance density C/A isobtained from C-V measurements, ε₀ is the vacuum permitivity and 3.9 isthe dielectric constant of silicon dioxide.

The results of the electrical measurements of the fabricated planarcapacitors from different deposition conditions of the CVD Ta₂ O₅ filmsare listed in Table 2. Typically, CVD Ta₂ O₅ films have a high leakageassociated with defects from oxygen vacancies, residual hydrogen carbon,and low work function of bottom electrodes. Low work function of bottomelectrodes result in high leakage due to Schottky emission leakagemechanisms for a Ta₂ O₅ metal insulator metal (MIM) capacitor.Apparently, only O₂ plasma treatment following Ta₂ O₅ deposition doesnot result in good electrical performance. Combining both of the O₂plasma treatment and O₃ anneal, however, dramatically reduces thecapacitor leakage. This reduction in turn increases the criticalvoltage. For high density DRAM applications such as 256 Meg DRAM, thecritical voltage should be 1.0 V or above. In addition, the T_(eff) isalso decreased possibly due to increase of Ta₂ O₅ dielectric constantand improvement of the bottom electrode interface. Two-step annealsrender the Ta₂ O₅ capacitor to reach the leakage requirements.Therefore, Ta₂ O₅ capacitors can be applied to DRAMs with a density of256 megabits or more.

                  TABLE 2                                                         ______________________________________                                        1           2      3       4    5    6     7                                  ______________________________________                                        Metal   sp-W    sp-W   sp-W  sp-W sp-W CVD W CVD W                              N.sub.2 plasma yes yes yes no no no no                                        400° C.                                                                RTN, yes yes yes yes yes yes yes                                              700° C.                                                                1 min.                                                                        NH.sub.3 gas                                                                  Bottom WN.sub.x WN.sub.x WN.sub.x WN.sub.x WN.sub.x WN.sub.x WN.sub.x                                                     Electrode                         Ta.sub.2 O.sub.5  400 400 400 450 450 480 480                                 growth                                                                        temp (° C.)                                                            O.sub.2 plasma yes yes yes yes yes yes yes                                    100 W                                                                         380° C.                                                                15 min.                                                                       O.sub.3 Anneal no yes yes no yes no yes                                       270° C.                                                                10 min.                                                                       Top Au Au Au Au Au Au Au                                                      Electrode                                                                     +V.sub.C (V) 1.28 2.07 1.41 0.80 1.79 shorted 1.72                            T.sub.eff (nm) 5.38 4.39 4.70 6.07 4.14 shorted 3.95                        ______________________________________                                    

FIG. 4 provides a table of results of further experimentation. Fortyexperimental devices were fabricated. Each of these are listed acrossthe top of the figure. Each of these wafers went through at least sixprocessing steps, namely 1.) wafer, 2.) tungsten formation, 3.)nitridation, 4.) Ta₂ O₅ deposition, 5.) O₂ plasma, and 6.) goldevaporation. These steps are listed down the side of the figure. Severalof the steps include more than one options. The filled in circleindicates which options were used for each of the forty wafers.

Reviewing the entries in the figure, the tungsten bottom electrode wasformed in one of three ways--sputtering, chemical vapor deposition, ordeposition by a replacement process using WF₆ gas. In this process,silicon is replaced by tungsten during reaction of WF₆ +Si→W+SiF_(x)where SiF_(x) is pumped away in the vapor phase. The nitridation stepscould be a rapid thermal nitridation, a nitrogen plasma or an ammoniaplasma.

The results of the experimentation is tabulated in Table 3

                                      TABLE 3                                     __________________________________________________________________________    Wafer #                                                                            1  2  3  4   5  6   7  8   9  10                                         __________________________________________________________________________      Teff(nm) 4.45 6.07 5.70 5.24 5.56 5.31 9.78 8.27 7.79 5.25                    +Vc 1.23 0.80 0.91 1.24 0.95 0.85 3.48 1.67 2.30 1.05                         -Vc 2.40 3.00 2.91 1.38 3.93 4.01 >5.0 >5.0 >5.0 4.65                       __________________________________________________________________________      Wafer # 11 12 13 14 15 16 17 18 19 20                                       __________________________________________________________________________      Teff(nm) 4.50 3.89 5.94 7.89 5.05 8.87 9.40 7.90 -- --                        +Vc 0.64 0.66 1.20 0.88 0.65 3.51 2.86 3.31 short short                       -Vc 2.89 3.20 >5.0 4.27 4.08 >5.0 >5.0 >5.0 short short                     __________________________________________________________________________      Wafer # 21 22 23 24 25 26 27 28 29 30                                       __________________________________________________________________________      Teff(nm) -- 7.22 7.35 5.43 6.87 8.45 5.64 4.14 4.94 3.95                      +Vc short 1.50 0.59 1.25 1.75 1.83 1.78 1.79 2.00 1.72                        -Vc short 4.50 1.79 2.97 >5.0 4.95 >5.0 >5.0 3.18 2.17                      __________________________________________________________________________      Wafer # 31 32 33 34 35 36 37 38 39 40                                       __________________________________________________________________________      Teff(nm) 6.29 6.92 7.56 5.21 7.06 5.38 5.50 6.81 5.90 5.61                    +Vc 2.42 2.15 2.35 4.15 1.90 2.38 2.87 2.90 0.85 0.69                         -Vc 3.50 4.73 short >5.0 >5.0 4.38 3.53 >5.0 3.80 2.00                      __________________________________________________________________________

From feasibility studies, all capacitors with a bottom electrodes usingsurface nitrided WN resulted in significant increase +E_(c) (=+V_(c)/T_(eff)) compared to capacitors using W bottom electrode. The NH₃-nitrided WN gave the highest +E_(c) of 4.2 MV/cm without O₃ anneal.With O₃ anneal, the +E_(c) has the highest value of 8 MV/cm. Therefore,based on feasibility studies and extrapolation, production qualitydevices should be able to meet the requirements of +Ec=5.0 MV/cm (+1.0Vc/2.0 nm).

The experimentation also led to the observation that RTN using NH₃ gasat 700° C. for one minute resulted in uniform ˜3.0 nm surface WN onsputtered W bottom electrodes. This result shows that surfacenitridation is a robust and manufacturable process.

Replacement W at 300° C. using HF wet cleaning and in-situ H₂ plasma forpre-cleaning had the best W layer in terms of wormhole formation,roughness, and W thickness compared to other deposition temperatures andpre-cleaning methods. However, replacement W at 300° C. still hadsignificant wormhole and encroachment which could be a key limitationfor manufacturing applications. To overcome this limitation, a metal SNwith an adhesion layer could be used.

Mechanistic studies of leakage conduction for MIM capacitors were alsoperformed. These studies confirmed Schottky emission for Ta₂ O₅ MIMcapacitor, thereby verifying the proposal that using WN and WSiNprovides for high work function and oxidation resistance. While O₃-anneal effects are still under further evaluation, initial results haveshown that an O₃ -anneal increases Schottky barrier height anddielectric constant, likely due to an increase in the oxygenconcentration. Therefore, the O₃ -anneal lowered the leakage as well asT_(eff). Two-step anneals with O₂ plasma and O₃ anneal have bothadvantages of high energy oxygen provided into Ta₂ O₅ films from O₂plasma and O₃ anneal to further supply oxygen due to low decompositionenergy barrier and to anneal out damage caused by O₂ plasma.

The method and structure of the present invention provide an integratedcircuit capacitor which can be used in a wide variety of applications.While described thus far in the context of a dynamic random accessmemory (DRAM), the present invention can also be used to form acapacitor for an analog-to-digital (A/D) converter, a digital-to-analog(D/A) converter, or just about any other integrated circuit chip

While this invention has been described with reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various modifications and combinations of theillustrative embodiments, as well as other embodiments of the invention,will be apparent to persons skilled in the art upon reference to thedescription. It is therefore intended that the appended claims encompassany such modifications or embodiments.

What is claimed is:
 1. A method of forming an integrated circuitcapacitor, the method comprising the steps of:forming a storage nodeelectrode; depositing a dielectric layer over the storage nodeelectrode; performing an O₂ plasma anneal after depositing thedielectric layer; performing an ozone anneal after performing the O₂plasma anneal; and depositing a top electrode over the dielectric layer.2. The method of claim 1 wherein the step of forming a storage nodeelectrode comprises forming a silicon storage node electrode.
 3. Themethod of claim 1 wherein the step of forming a storage node electrodecomprises forming a metal storage node electrode.
 4. The method of claim1 wherein the step of forming a storage node electrode comprises forminga ceramic storage node electrode.
 5. The method of claim 1 wherein thestep of depositing a dielectric layer comprises depositing a tantalumpentoxide layer.
 6. The method of claim 1 wherein the step of depositinga dielectric layer comprises depositing a lead zirconium titanate layer.7. The method of claim 1 wherein the step of depositing a dielectriclayer comprises depositing a barium strontium titanate layer.
 8. Themethod of claim 1 wherein the step of depositing a dielectric layercomprises depositing a strontium titanate layer.
 9. The method of claim1 wherein the step of depositing a dielectric layer comprises depositinga high dielectric constant material.
 10. The method of claim 1 whereinthe step of depositing a dielectric layer comprises depositing adielectric derived from a material organic source.
 11. The method ofclaim 1 wherein the ozone anneal is performed in the presence of ultraviolet light irradiation.
 12. The method of claim 1 wherein the ozoneanneal is performed without ultra violet light irradiation.
 13. Themethod of claim 1 and further comprising the step of performing acrystallization anneal prior to the step of performing an ozone anneal.